
Alignments
EN 57SDI PDP 8.
8.3 Alignments 42” SD v3
1. Put the dipswitches on the Logic Board in the internal
position to get a Full White Pattern.
2. You can find the location of the test point and
potentiometers in Figure “Potentiometer locations”.
3. Adjust Vsch to 40 V with VR5004.
4. Check the waveform with an Oscilloscope.
• Take the trigger signal from the testpoint marked “V-
sync” on the Logic Board.
• Connect the testpoint marked “OUT 4”, located in the
centre of Y_buffer Board to the other channel, and then
check the first Subfield operating waveform of one TV-
Field.
• Check the waveform again after adjusting Horizontal
Division. Check the Reset waveform when the
V_TOGG Level is changed.
• Set the Vset to 10µs by adjusting VR5002.
• Set the Falling maintenance time to 30 µs by adjusting
VR5003.
• Change the waveform position of Oscilloscope to the
3rd Subfield and then set the Falling maintenance time
to 30µsby adjusting the VR5001. GND maintenance
section should be checked after the Vertical Division is
readjusted to '2 V or 5 V'.
Special notice: It is very important, that you execute this
adjustment on the 1st Sub-Field (SF) of the 1st Frame of the
Reset waveform and then move to the 3rd Sub-field for
adjusting.
Figure 8-13 DIP switch mode: External
Figure 8-14 DIP switch mode: Internal
Figure 8-15 TCP ramp waveform inclination adjustment (Y-Board)
1 2 3 4
1
2
3
4
Adjust VR5003 to set the time of
Yfr (Falling Ramp_1st) 30
µs
Adjust VR5002 to set the time of
Yrr (Rising Ramp) 10
µs
Adjust VR5001 to set the time of
Yfr (Falling Ramp_3rd) 30
µs
Adjust VR5004 to set the voltage of
Vsch (Scan high voltage) 40 V
rising maintenance time
falling maintenance time
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